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47
CY29947
2.5V or 3.3V, 200-MHz, 1:9 Clock Distribution Buffer
Features
* * * * * * * * * * 2.5V or 3.3V operation 200-MHz clock support LVCMOS-/LVTTL-compatible inputs 9 clock outputs: drive up to 18 clock lines Synchronous Output Enable Output three-state control 250 ps max. output-to-output skew Pin compatible with MPC947, MPC9447 Available in Industrial and Commercial temp. range 32-pin TQFP package
Description
The CY29947 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible clock inputs. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The 9 outputs are LVCMOS or LVTTL compatible and can drive 50 series or parallel terminated transmission lines.For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the CY29947 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The CY29947 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated.
Block Diagram
Pin Configuration
VDDC VDDC 27 VSS VSS VSS 25 24 23 22 21 20 19 18 17 Q0 Q1 28 Q2 26
VDD TCLK0 TCLK1 TCLK_SEL SYNC_OE TS# 0 1
VDDC
32 31 30 VSS TCLK_SEL TCLK0 TCLK1 SYNC_OE TS# VDD VSS 1 2 3 4 5 6 7 8 29 VSS Q3 VDDC Q4 VSS Q5 VDDC VSS
9
Q0-Q8
CY29947
10 11 12 13 14 VDDC 15 Q6 16 VSS 9 VSS
VSS
Q8
Cypress Semiconductor Corporation Document #: 38-07287 Rev. *C
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3901 North First Street
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San Jose
VDDC
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CA 95134 * 408-943-2600 Revised December 22, 2002
Q7
CY29947
Pin Description[1]
Pin 3 4 2 11, 13, 15, 19, 21, 23, 26, 28, 30 5 6 10, 14, 18, 22, 27, 31 7 1, 8, 9, 12, 16, 17, 20, 24, 25, 29, 32 Name TCLK0 TCLK1 TCLK_SEL Q(8:0) VDDC PWR I/O I, PU I, PU I, PU O Test Clock Input Test Clock Input Test Clock Select Input. When LOW, TCLK0 is selected. When asserted HIGH, TCLK1 is selected. Clock Outputs Description
SYNC_OE TS# VDDC VDD VSS
I, PU I, PU
Output Enable Input. When asserted HIGH, the outputs are enabled and when set LOW the outputs are disabled in a LOW state. Three-state Control Input. When asserted LOW, the output buffers are three-stated. When set HIGH, the output buffers are enabled. 3.3V or 2.5V Power Supply for Output Clock Buffers 3.3V or 2.5V Power Supply Common Ground
Note: 1. PD = internal pull-down, PU = internal pull-up.
Output Enable/Disable
The CY29947 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown in Figure 1.
TCLK SYNC_OE
Q
Figure 1. SYNC_OE Timing Diagram
Document #: 38-07287 Rev. *C
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CY29947
Maximum Ratings [2]
Maximum Input Voltage Relative to VSS: ............. VSS - 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ -65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum ESD protection ................................................ 2kV Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
DC Parameters: VDD = VDDC = 3.3V 10% or 2.5V 5%, Over the specified temperature range
Parameter VIL VIH IIL IIH VOL VOH IDDQ IDD Description Input Low Voltage Input High Voltage Input Low Current[3] Voltage[4] Voltage[4] IOL = 20 mA IOH = -20 mA, VDD = 3.3V IOH = -20 mA, VDD = 2.5V Quiescent Supply Current Dynamic Supply Current VDD = 3.3V, Outputs @ 100 MHz, CL = 30 pF VDD = 3.3V, Outputs @ 160 MHz, CL = 30 pF VDD = 2.5V, Outputs @ 100 MHz, CL = 30 pF VDD = 2.5V, Outputs @ 160 MHz, CL = 30 pF Zout Cin Output Impedance Input Capacitance VDD = 3.3V VDD = 2.5V 12 14 2.5 1.8 5 120 200 85 140 15 18 4 18 22 pF 7 mA mA Input High Current[3] Output Low Output High Conditions Min. VSS 2.0 Typ. Max. 0.8 VDD -100 10 0.4 Unit V V A A V V
Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines.
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CY29947
AC Parameters[5]: VDD = VDDC = 3.3V 10% or 2.5V 5%, Over the specified temperature range
Parameter Fmax Tpd FoutDC tpZL, tpZH tpLZ, tpHZ Tskew Tskew(pp) Ts Th Tr/Tf Description Input Frequency
[6]
Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V Measured at VDD/2
Min.
Typ.
Max. 200 170
Unit MHz ns % ns ns ps ns ps ps
TCLK To Q Delay[6] Output Duty Cycle
[6, 7]
4.75 6.50 45 2 2 150
9.25 10.50 55 10 10 250 2.0
Output Enable Time (all outputs) Output Disable Time (all outputs) Output-to-Output Skew Part-to-Part Skew Set-up Time[6, 10] Hold Time
[6, 10] [8] [9] [6, 8]
SYNC_OE to TCLK TCLK to SYNC_OE 0.8V to 2.0V, VDD = 3.3V 0.6V to 1.8V, VDD = 2.5V
0.0 1.0 0.20 0.20 1.0 1.3
Output Clocks Rise/Fall Time
ns
Notes: 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 6. Outputs driving 50 transmission lines. 7. 50% input duty cycle. 8. See Figure 2. 9. Part-to-Part skew at a given temperature and voltage. 10. Set-up and hold times are relative to the falling edge of the input clock
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CY29947
CY29947 DUT
Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 2. LVCMOS_CLK CY29947 Test Reference for VCC = 3.3V and VCC = 2.5V
LVCMOS_CLK
VCC VCC /2 GND VCC
Q
VCC /2
tPD
GND
Figure 3. LVCMOS Propagation Delay (TPD) Test Reference
VCC VCC /2
tP
T0
GND
DC = tP / T0 x 100%
Figure 4. Output Duty Cycle (FoutDC)
VCC VCC /2 GND VCC VCC /2
tSK(0)
Figure 5. Output-to-Output Skew tsk(0).
GND
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CY29947
Ordering Information
Part Number CY29947AI CY29947AIT CY29947AC CY29947ACT Package Type 32 Pin TQFP 32 Pin TQFP - Tape and Reel 32 Pin TQFP 32 Pin TQFP - Tape and Reel Production Flow Industrial, -40C to +85C Industrial, -40C to +85C Commercial, 0C to +70C Commercial, 0C to +70C
Package Drawing and Dimensions
32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32
51-85063-*B
All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY29947
Revision History
Document Title: CY29947 2.5V or 3.3V, 200-MHz, 1:9 Clock Distribution Buffer Document Number: 38-07287 REV. ** *A *B *C ECN NO. 111098 116781 118462 122879 Issue Date 02/07/02 08/14/02 09/09/02 12/22/02 Orig. of Change BRK HWT HWT RBI New data sheet Added Commercial Temperature Range in the ordering information Corrected the Package Drawing and Dimension in page 6 from 32 LQFP to 32 TQFP Added power up requirements to Maximum Ratings Description of Change
Document #: 38-07287 Rev. *C
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